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Text File  |  1996-11-16  |  1KB  |  23 lines
  1. Begin3
  2. Title:          Verilog Behavioral Simulator (VBS)
  3. Version:        1.3.0 (alpha)
  4. Entered-date:   June 29, 1996
  5. Description:    Simulator for Verilog HDL.  Supports functions, tasks
  6.                 and module instantiation.  Still lacks a lot of features,
  7.                 but this release has enough for a VLSI student to use
  8.                 and learn Verilog.  Supports only behavioral constructs
  9.                 of Verilog and minimal simulation constructs such as
  10.                 'initial' statements.  This version has some additional
  11.                 features.  See the README file for more details.
  12. Keywords:       Verilog, HDL, circuit, simulator
  13. Author:         jching@aloha.com (Jimen Ching)
  14. Maintained-by:  jching@aloha.com (Jimen Ching)
  15. Primary-site:   sunsite.unc.edu /pub/Linux/apps/circuits
  16.                   128kB vbs-1.3.0.tar.gz
  17.                   1kB vbs-1.3.0.lsm
  18. Alternate-site: Not Yet Available
  19. Original-site:  None
  20. Platform:       C, C++, flex, bison
  21. Copying-policy: GPL
  22. End
  23.